//------------------------------------------------------------
//  Filename: video_scaler.v
//   
//  Author  : wlduan@gmail.com
//  Revise  : 2016-10-17 09:52
//  Description: 
//   
//  Copyright (C) 2014, YRBD, Inc. 					      
//  All Rights Reserved.                                       
//-------------------------------------------------------------
//
`timescale 1ns/1ps
 
module VIDEO_SCALER ( 
    input  wire        clk_100mhz,
    input  wire        rst,

    input  wire [15:0] x_org_cnt,
    input  wire [15:0] y_org_cnt,
    input  wire [15:0] x_scaler,
    input  wire [15:0] y_scaler,
    
    // User fifo in
    input  wire        sensor_wr_en,
    input  wire [32:0] sensor_din,

    // User fifo out
    output reg         camera_wr_en,
    output reg  [32:0] camera_din    
);      
//--------------------------------------------------------
wire   clk = clk_100mhz;
//--------------------------------------------------------
reg[15:0] x_cntr;
reg[15:0] y_cntr;
reg[15:0] x_scaler_cntr;
reg[15:0] y_scaler_cntr;
reg[32:0] sensor_din_ff1;
reg       sensor_wr_en_ff1;
//--------------------------------------------------------
always @(posedge clk,posedge rst) begin
    if(rst)begin 
        x_cntr <= 16'h0;    
        x_scaler_cntr <= 16'b0;        
    end 
    else if(sensor_din[32] == 1'b1)begin 
        x_cntr <= 16'h1;    
        x_scaler_cntr <= 16'b1;        
    end 
    else if(sensor_wr_en) begin
        x_cntr <= (x_cntr < x_org_cnt)? (x_cntr + 16'h1):16'h1;    
        x_scaler_cntr <= (x_scaler_cntr < x_scaler)? (x_scaler_cntr + 16'h1):16'h1;
    end
end 
//--------------------------------------------------------
wire new_line = (x_cntr == 1)?1'b1:1'b0;
//--------------------------------------------------------
always @(posedge clk,posedge rst) begin
    if(rst)begin 
        y_cntr <= 16'h0;    
        y_scaler_cntr <= 16'b0;        
    end 
    else if(sensor_din[32] == 1'b1)begin 
        y_cntr <= 16'h0;    
        y_scaler_cntr <= 16'b0;        
    end 
    else if((new_line == 1'b1)&&sensor_wr_en) begin
        y_cntr <= y_cntr + 16'h1;    
        y_scaler_cntr <= (y_scaler_cntr < y_scaler)? (y_scaler_cntr + 16'h1):16'h1;
    end
end 
//--------------------------------------------------------
always @(posedge clk,posedge rst) begin
    if(rst)begin 
        sensor_din_ff1   <= 33'h0;    
        sensor_wr_en_ff1 <= 1'b0;
    end 
    else begin 
        sensor_din_ff1   <= {sensor_din[32],sensor_din[7:0],sensor_din[7:0],sensor_din[7:0],sensor_din[7:0]}; 
        sensor_wr_en_ff1 <= sensor_wr_en;
    end 
end 
//--------------------------------------------------------
always @(posedge clk,posedge rst) begin
    if(rst)begin 
        camera_wr_en <= 1'b0;  
        camera_din   <= 33'b0;
    end 
    else if(sensor_din_ff1[32] == 1'b1)begin
        camera_din   <= sensor_din_ff1;
        camera_wr_en <= 1'b1;        
    end
    else if((x_scaler_cntr == x_scaler)&&(y_scaler_cntr == y_scaler)&&(sensor_wr_en_ff1 == 1'b1)) begin 
        camera_din   <= sensor_din_ff1;
        camera_wr_en <= 1'b1;        
    end 
    else begin
        camera_wr_en <= 1'b0;        
    end
end 
 

endmodule
